The invention relates to the field of fabricating semiconductor devices and other electronic devices and in particular to a planarization method used for the formation of semiconductor devices.
The manufacture of integrated circuits in a semiconductor device involves the sequential deposition of layers in which patterns are formed. A pattern is first formed by a lithography process in a photoresist layer and is subsequently transferred into one or more layers in a substrate by an etching method. Alternately, the photoresist pattern can serve as a mask for an ion implant step. In either case, an important requirement of the photoresist layer is forming a planar surface in order to afford a large process latitude for the patterning step.
Often the substrate upon which the photoresist is spin coated is not planar because it may be comprised of a pattern containing features such as lines that protrude above the surface of the substrate. Other substrates may have a largely level surface except for contact holes or trenches that are etched below the surface. The topography of non-planar substrates can involve thickness variations as large as 1 micron or more. However, even substrate thickness differences of only 0.1 to 0.2 microns can be significant when considering that photoresist film thickness is becoming thinner as feature size decreases. For advanced technology nodes where the critical dimension of a line width or space width is less than 200 nm, most photoresist layers are in the range of about 2000 to 8000 Angstroms (0.2 to 0.8 micron) thick. A photoresist composition normally includes an organic solvent, a photosensitive compound, and a polymer that has a low molecular weight which flows easily and tends to planarize readily on relatively smooth surfaces. However, when the topography includes steps with a height that is more than about 10 to 20% of the photoresist film thickness, then planarization of the photoresist film is difficult.
The photoresist film is exposed with radiation from an exposure source such as an excimer laser or a broadband Hg/Xe lamp that passes through a mask containing the device pattern to be reproduced on the substrate. The mask has a patterned opaque coating such as chrome on a transparent substrate like quartz. A good lithography process is defined as one that has a manufacturable process window in which there is a wide dose latitude and focus latitude for printing the pattern in the photoresist film. Generally, a depth of focus (DOF) of about 0.4 to 1 micron and a dose latitude of at least 10 to 20% is desirable for maintaining a printed feature size within xc2x110% of a targeted value. One can appreciate that if the photoresist layer has a thickness variation of 0.1 micron or more, then a significant portion of the DOF budget has been consumed by material aspects and not by the exposure process itself. Typically, the spin coating process is optimized so that the photoresist thickness variation is minimized to a value of less than 10 Angstroms across the wafer. This is accomplished on planar substrates by varying the spin speed during the coating process and by wetting the substrate with a solvent prior to applying the photoresist solution.
The relationship of photoresist thickness to the radiation dose or energy required to print a pattern in the film is provided in FIG. 1. The plot of thickness vs. dose forms a sinusoidal curve 5 that has minima 1, 3 and maxima 2, 4. This xe2x80x9cswingxe2x80x9d curve has an amplitude A between a minimum and a maximum energy and a periodicity B defined as the distance (thickness) between two adjacent minimum points or two adjacent maximum points on the curve 5. The magnitude of periodicity B is related to the wavelength of the exposing radiation. The amplitude A is calculated by dividing the difference between the energy for maximum point 2 (E2) and the energy for minimum point 1 (E1) by the average of E1 and E2 which is (E2xe2x88x92E1)/(E1+E2/2) and this value can be as large as 0.3 which is a swing of 30% in dose.
The swing effect is caused because radiation that passes through the photoresist is partially reflected off the underlying layer and can either constructively or destructively interfere with radiation making a first pass through the photoresist. The extent of constructive or destructive interference depends upon the thickness of the film and the wavelength of the radiation. The swing amplitude has a detrimental effect on the patterning process, especially if it is more than a few % of the average dose. Consider the condition in FIG. 1 where a swing amplitude of 30% is realized as determined previously for E1 and E2 and the patterned feature is a contact hole. If a dose E1 is used to form a contact hole in a photoresist that has a region with a thickness T1 and a region with a thickness T2, then the size of the hole with thickness T1 will be much larger than the hole size with thickness T2 since the latter requires a much higher energy to form a hole to a predetermined size. The size difference in space width of the hole is likely to be much greater than the xc2x110% specification described earlier for a manufacturing process.
In some situations, an anti-reflective coating (ARC) is applied to the substrate prior to the photoresist coating in order to control reflectivity during the photoresist exposure step and enable a larger process latitude by reducing the swing effect. The ARC which can be an organic or inorganic material is normally much thinner than the photoresist and is most effective on relatively flat substrates. While some organic ARCs have been developed for spin coating over features such as contact holes, there are none available that can completely planarize a surface with topography variations of about 0.1 microns or larger.
Planarization methods have been proposed for different applications in prior art. In U.S. Pat. No. 5,077,234, a process is provided for filling STI trenches of varying widths. The method requires three photoresist layers. A first photoresist is patterned to fill only large trenches of greater than 30 microns in width. This photoresist plug is then hardened by a combination of heating to 200xc2x0 C. and UV exposure. A second photoresist is coated and baked to  greater than 150xc2x0 C. and then etched back until the layer is removed over active regions. Then a third photoresist layer is coated and etched back to form a planar layer.
In U.S. Pat. No. 6,008,105, a process is described for planarizing a depression formed in an insulating layer that is deposited over interconnect lines. A mask pattern is used to selectively leave photoresist that fills the depression. The photoresist is baked at 150xc2x0 C. to remove solvent and then cured by UV radiation. A second photoresist is coated on the substrate and etched back to form a planar surface. This technique requires a new mask to be built for each pattern of interconnect lines and can be expensive since several metal layers are present in a device.
U.S. Pat. No. 5,618,751 describes a method of forming a trench capacitor that requires a photoresist to be coated over a trench that is  less than 0.5 microns wide. Since the opening is small, the photoresist does not fill the trench and must be heated above its softening point so that it flows into the trench. The photoresist is preferably exposed with an electron beam source to avoid diffraction effects and formation of standing waves on the sidewalls of the trench. The photoresist is developed to form a recessed layer within the trench that serves as an etch stop for etching an adjacent diffusion source layer to a prescribed depth. A point is made that the electron beam exposure yields a more planar photoresist surface within the trench than photolithography with Deep UV (248 nm), i-line (365 nm) or mid UV (435 nm) radiation sources. However, this patent does not mention a solution for forming a planar photoresist over a substrate that has both isolated and dense trench patterns.
Other background art found in U.S. Pat. No. 6,218,196 deals with a problem of etching a pattern that contains both dense and isolated lines. The space between dense lines etches slower than the region along isolated lines and creates a reactive ion etch (RIE) lag. An apparatus and etching method are provided that includes a deposition gas such as CHF3 that forms a protective layer on the photoresist sidewalls to prevent notching and an etching gas mixture of Cl2 and BCl3. The reactive products from CHF3 and Clxe2x88x92 excessively react at isolated lines to produce a higher deposition rate that decreases the etch rate difference between isolated and dense lines.
Besides the planarization requirement cited previously for dielectric layers on interconnect lines, for filling STI trenches, and for forming trench capacitors, another application shown in FIG. 2 that needs a planar photoresist layer is a dual damascene process in which a trench is patterned above a substrate 10 and etch stop layer 11 that includes both isolated 13a and dense via holes 13b-13e in dielectric layer 12. In this case, the photoresist 14 thickness over the dense via hole region is thinner than over the isolated hole 13a because a considerable amount of photoresist is used to fill the dense holes 13b-13e. The difference in photoresist thickness is represented by the distance D1 and can be over 2000 Angstroms. This is a large variation that can reduce DOF for the patterning process and result in a large difference in trench opening sizes that are formed above the holes. One current solution to the problem that is practiced by the inventors is to etch back the photoresist 14 and repeat the photoresist coating and etch back process several times in order to form a planar photoresist. However, this is costly in terms of slow throughput as well as material and equipment usage. An improved method is needed that has faster throughput and has a minimal cost impact on the manufacturing scheme.
An objective of the present invention is to provide a photoresist planarization process that is low cost and can be readily implemented in a manufacturing environment.
A further objective of the present invention is to provide a photoresist planarization method that can be used in a dual damascene process where trenches are patterned above both isolated and dense via holes in the same pattern.
A still further objective of the present invention is to provide a planarization method that can be applied to fabricating metal-insulator-metal capacitors in which contact holes having regions of low and high duty ratios exist in the same pattern.
According to one embodiment, these objectives are accomplished by providing a substrate that has a patterned dielectric layer comprised of both isolated and dense via holes formed thereon. A first photoresist layer is spin coated on the dielectric layer and baked at a high enough temperature so that the photoresist reflows into the holes and thereby forms an uneven thickness above the dielectric layer. The photoresist is blanket exposed without a mask and is developed to remove all photoresist above the dielectric layer and form a recessed layer of photoresist within the holes. A high temperature bake of 250xc2x0 C. is performed to remove any remaining solvent in the photoresist and to harden the film. Preferably, the photoresist is comprised of a Novolac resin and a diazonaphthoquionone photoactive compound which form a crosslinked network that becomes impervious to organic materials or solvents that are coated on it. Then a second photoresist is spin coated on the dielectric layer having holes containing the recessed hardened photoresist to form a planar layer that can be controllably patterned with trenches that are aligned above the contact holes. Conventional processing is then followed to form metal interconnects.
In a second embodiment that relates to metal-insulator-metal (MIM) capacitor technology, a substrate is provided with a dielectric layer having contact hole regions with different duty ratios in which a bottom electrode such as TiN has been deposited. A first photoresist layer is spin coated and baked at a high enough temperature so that the photoresist reflows into the holes and thereby forms an uneven thickness above the metal layer. The photoresist is blanket exposed without a mask and developed to remove all photoresist above the metal layer except for a recessed layer of photoresist within the holes. A high temperature bake of 250xc2x0 C. is performed to remove any remaining solvent and to harden the film. Preferably, the photoresist includes a Novolac resin and a diazonaphthoquionone photoactive compound which form a crosslinked network that becomes impervious to organic materials or solvents that are coated on it. Then a second photoresist is spin coated on the metal layer and covers the holes containing the recessed hardened photoresist to form a planar layer. The photoresist is then etched back until it forms a recessed layer within the holes. A second etch is then performed to etch back the TiN layer until it is about coplanar with the recessed photoresist layer. The remaining photoresist is then removed by a plasma ashing process and conventional processing is followed to complete the MIM capacitor.